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Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
ISL6420A
The ISL6420A simplifies the implementation of a complete control and protection scheme for a high-performance DC/DC buck converter. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The ISL6420A integrates control, output adjustment, monitoring and protection functions into a single package. Additionally, the IC features an external reference voltage tracking mode for externally referenced buck converter applications and DDR termination supplies, as well as a voltage margining mode for system testing in networking DC/DC converter applications. The ISL6420A provides simple, single feedback loop, voltage mode control with fast transient response. The output voltage of the converter can be precisely regulated to as low as 0.6V. The operating frequency is fully adjustable from 100kHz to 1.4MHz. High frequency operation offers cost and space savings. The error amplifier features a 15MHz gain-bandwidth product and 6V/s slew rate that enables high converter bandwidth for fast transient response. The PWM duty cycle ranges from 0% to 100% in transient conditions. Selecting the capacitor value from the ENSS pin to ground sets a fully adjustable PWM soft-start. Pulling the ENSS pin LOW disables the controller. The ISL6420A monitors the output voltage and generates a PGOOD (power good) signal when soft-start sequence is complete and the output is within regulation. A built-in overvoltage protection circuit prevents the output voltage from going above typically 115% of the set point. Protection from overcurrent conditions is provided by monitoring the rDS(ON) of the upper MOSFET to inhibit the PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sensing resistor.
ISL6420A
Features
* Operates From: - 4.5V to 5.5V Input - 5.5V to 28V Input * 0.6V Internal Reference Voltage - 1.0% Reference Accuracy * Resistor-Selectable Switching Frequency - 100kHz to 1.4MHz * Voltage Margining and External Reference Tracking Modes * Output can Sink or Source Current * Lossless, Programmable Overcurrent Protection - Uses Upper MOSFET's rDS(ON) * Programmable Soft-Start * Drives N-Channel MOSFETs * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle * Extensive Circuit Protection Functions - PGOOD, Overvoltage, Overcurrent, Shutdown * Diode Emulation during Startup for Pre-Biased Load Applications * Offered in 20 Ld QFN and QSOP Packages * QFN (4x4) Package - QFN compliant to JEDEC PUB95 MO-220 QFN -Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile * Pb-Free (RoHS Compliant)
Applications
* Power Supplies for Microprocessors/ASICs - Embedded Controllers - DSP and Core Processors - DDR SDRAM Bus Termination * Ethernet Routers and Switchers * High-Power DC/DC Regulators * Distributed DC/DC Power Architecture * Personal Computer Peripherals * Externally Referenced Buck Converters
December 4, 2009 FN9169.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6420A
Ordering Information
PART NUMBER (Notes 2, 3) ISL6420AIAZ ISL6420AIAZ-TK (Note 1) ISL6420AIRZ ISL6420AIRZ-TK (Note 1) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6240A For more information on MSL please see techbrief TB363. PART MARKING 6420 AIAZ 6420 AIAZ 64 20AIRZ 64 20AIRZ TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 20 Ld QSOP 20 Ld QSOP (Tape and Reel) 20 Ld 4x4 QFN 20 Ld 4x4 QFN (Tape and Reel) PKG. DWG. # M20.15 M20.15 L20.4x4 L20.4x4
Pin Configurations
ISL6420A (20 LD QFN) TOP VIEW
PHASE LGATE UGATE BOOT PVCC CDEL PGND LGATE 15 PGND 14 CDEL 13 PGOOD 12 ENSS 11 COMP 6 VCC5 7 VIN 8 SGND 9 RT 10 FB PVCC PHASE UGATE BOOT GPIO2 GPIO1/REFIN
ISL6420A (20 LD QSOP) TOP VIEW
1 2 3 4 5 6 7 8 9 20 PGOOD 19 ENSS 18 COMP 17 FB 16 RT 15 SGND 14 VIN 13 VCC5 12 VMSET/MODE 11 REFOUT
20 GPIO2 GPIO1/REFIN OCSET REFOUT VMSET/MODE 1 2 3 4 5
19
18
17
16
OCSET 10
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Block Diagram
ENSS VCC5 VIN
10A REFOUT ENSS INTERNAL 0.6V POWER-ON RESET (POR)
INTERNAL SERIES LINEAR OCSET OTP 100A
3
GPIO1/REFIN GPIO2 VMSET/MODE CDEL FB COMP PGOOD
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SSDONE
BOOT UGATE FAULT LOGIC SSDONE
SSDONE VOLTAGE MARGINING CONTROL
ISL6420A
GATE CONTROL LOGIC PWM COMP EA
PHASE
VREF
SS
PVCC
LGATE
PGND OSCILLATOR OV/UV COMP
PGOOD COMP
SGND
RT
EP (QFN ONLY)
ISL6420A
Typical 5V Input DC/DC Application Schematic
5V 10% C1 C2 VIN VCC5 C3 PVCC OCSET BOOT Q1 OSC REF + + VMSET/MODE REFOUT LGATE PGND GPIO1/REFIN GPIO2 Q2 C10 UGATE PHASE C9 L1 VOUT R1 C4 C5 D1 C6
ENSS RT C7 0.1F R2 C8 PGOOD CDEL SGND FB R3 + -
MONITOR AND PROTECTION
C11 COMP R5 R4 C12
R6
C13
VOLTAGE MARGINING ENABLED WITH INTERNAL VREF SEE PAGE 12 FOR MORE DETAILS
Typical 5.5V to 28V Input DC/DC Application Schematic
5.5V to 28V C1 C2 VIN VCC5 C3 PVCC OCSET BOOT UGATE PHASE REF SGND FB R3 + C11 R5 R4 COMP + + REFOUT VMSET/MODE LGATE PGND GPIO1/REFIN GPIO2 Q2 C10 Q1 C9 L1 VOUT R1 C4 C5 D1 C6
ENSS RT C7 0.1F PGOOD R2 C8 CDEL
MONITOR AND PROTECTION
OSC
C12
R6
C13
VOLTAGE MARGINING ENABLED WITH INTERNAL VREF SEE PAGE 12 FOR MORE DETAILS
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ISL6420A
Typical 5V Input DC/DC Application Schematic
5V 10% C1 C2 VIN PVCC C3 VCC5 OCSET BOOT UGATE PHASE REF SGND FB R3 + C10 C11 R4 COMP + LGATE PGND REFOUT Q2 C9 Q1 C8 L1 2.5V/1.25V R1 C4 C5 D1 C6
ENSS RT CDEL C7 R2 PGOOD
MONITOR AND PROTECTION
OSC
VMSET/MODE
GPIO2
GPIO1/REFIN <-- VREF = VDDQ/2 1.25V VREF TO REFIN OF VTT SUPPLY
R5
C12
VCC5 CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS
Typical 5.5V to 28V Input DC/DC Application Schematic
5.5V to 28V C1 C2 VIN VCC5 C3 PVCC OCSET BOOT Q1 OSC REF SGND FB R3 + C10 C11 COMP + LGATE PGND REFOUT GPIO2 Q2 C9 UGATE PHASE C8 L1 2.5V/1.25V R1 C4 C5 D1 C6
ENSS RT CDEL C7 R2 PGOOD
MONITOR AND PROTECTION
VMSET/MODE
GPIO1/REFIN <-- VREF = VDDQ/2 1.25V VREF TO REFIN OF VTT SUPPLY
R5
R4
VCC5 CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS
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Typical 5V Input DC/DC Application Schematic
5V 10% C1 C2 VIN VCC5 C3 PVCC OCSET BOOT UGATE PHASE REF SGND FB R3 + C11 R5 R4 COMP + + VMSET/MODE GPIO1/REFIN GPIO2 REFOUT LGATE PGND Q2 C10 Q1 C9 L1 VOUT R1 C4 C5 D1 C6
ENSS RT C7 0.1F PGOOD R2 C8 CDEL
MONITOR AND PROTECTION
OSC
C12
C13
USE INTERNAL VREF WITH NO VOLTAGE MARGINING SEE PAGE 12 FOR MORE DETAILS
Typical 5.5V to 28V Input DC/DC Application Schematic
5.5V to 28V C1 C2 VIN VCC5 C3 PVCC OCSET ENSS RT C7 0.1F PGOOD R2 C8 CDEL REF SGND FB R3 + C11 R5 R4 COMP + + REFOUT VMSET/MODE GPIO1/REFIN GPIO2 LGATE PGND Q2 C10 OSC MONITOR AND PROTECTION BOOT UGATE PHASE Q1 C9 L1 VOUT R1 C4 C5 D1 C6
C12
C13
USE INTERNAL VREF WITH NO VOLTAGE MARGINING SEE PAGE 12 FOR MORE DETAILS
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ISL6420A
Absolute Maximum Ratings (Note 4)
Bias Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V BOOT and UGATE Pins . . . . . . . . . . . . . . . . . . . . . . . . . +36V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) QFN Package (Notes 5, 6) . . . . . . . 47 8.5 QSOP Package (Note 5) . . . . . . . . 90 NA Maximum Junction Temperature (Plastic Package) . . +150C Maximum Storage Temperature Range . . . -65C to +150C Ambient Temperature Range . -40C to +85C (for "I" suffix) Junction Temperature Range . . . . . . . . . . -40C to +125C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. All voltages are with respect to GND. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VIN = 12V, PVCC shorted with VCC5, TA = +25C. Boldface limits apply over the operating temperature range, -40C to +85C. SYMBOL TEST CONDITIONS MIN (Note 12) TYP MAX (Note 12) UNITS
PARAMETER VIN SUPPLY Input Voltage Range VIN SUPPLY CURRENT Shutdown Current (Note 7) Operating Current (Notes 7, 8) VCC5 SUPPLY (Notes 8, 9) Input Voltage Range Output Voltage Maximum Output Current POWER-ON RESET Rising VCC5 Threshold Falling VCC5 Threshold UVLO Threshold Hysteresis PWM CONVERTERS Maximum Duty Cycle Minimum Duty Cycle FB Pin Bias Current Undervoltage Protection Overvoltage Protection OSCILLATOR Free Running Frequency Total Variation Frequency Range (Set by RT) Ramp Amplitude (Note 10)
5.6
12
28
V
ENSS = GND
-
1.4 2.0
3.0
mA mA
VIN = VCC5 for 5V configuration VIN = 5.6V to 28V, IL = 3mA to 50mA VIN = 12V
4.5 4.5 50
5.0 5.0 -
5.5 5.5 -
V V mA
VIN connected to VCC5, 5V input operation
4.310 4.090 0.16
4.400 4.100 -
4.475 4.250 -
V V V
fSW = 300kHz fSW = 300kHz
90 -
96 80 -
0 85 120
% % nA % %
VUV VOVP
Fraction of the set point; ~3s noise filter Fraction of the set point; ~1s noise filter
75 112
RT = VCC5, TA = -40C to +85C TA = -40C to +85C, with frequency set by external resistor at RT VIN = 12V VOSC
270 100 -
300 10% 1.25
330 1400 -
kHz % kHz VP-P
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Electrical Specifications
Operating Conditions: VIN = 12V, PVCC shorted with VCC5, TA = +25C. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) SYMBOL TEST CONDITIONS MIN (Note 12) TYP MAX (Note 12) UNITS
PARAMETER
REFERENCE AND SOFT-START/ENABLE Internal Reference Voltage Soft-Start Current Soft-Start Threshold Enable Low (Converter Disabled) PWM CONTROLLER GATE DRIVERS Gate Drive Peak Current Rise Time Fall Time Dead Time Between Drivers ERROR AMPLIFIER DC Gain (Note 10) Gain-Bandwidth Product (Note 10) Slew Rate (Note 10) COMP Souce/Sink Current (Note 10) OVERCURRENT PROTECTION OCSET Current Source IOCSET VOCSET = 4.5V 80 100 120 A GBW SR 88 15 6 0.4 dB MHz V/s mA Co = 1000pF Co = 1000pF 0.7 20 20 20 A ns ns ns VREF ISS VSOFT 0.594 1.0 10 0.606 1.0 V A V V
POWER-GOOD AND CONTROL FUNCTIONS Power-Good Lower Threshold Power-Good Higher Threshold PGOOD Leakage Current PGOOD Voltage Low PGOOD Delay CDEL Current for PGOOD CDEL Threshold EXTERNAL REFERENCE Min External Reference Input at GPIO1/REFIN Max External Reference Input at GPIO1/REFIN REFERENCE BUFFER Buffered Output Voltage Internal Reference Buffered Output Voltage Internal Reference Buffered Output Voltage External Reference Buffered Output Voltage External Reference VREFOUT VREFOUT VREFOUT VREFOUT IREFOUT = 1mA,VMSET/MODE = High, CREFOUT = 2.2F, TA = -40C to +85C IREFOUT = 20mA,VMSET/MODE = High, CREFOUT = 2.2F, TA = -40C to +85C VREFIN = 1.25V, IREFOUT = 1mA, VMSET2/MODE = High, CREFOUT = 2.2F VREFIN = 1.25V, IREFOUT = 20mA, VMSET2/MODE = High,CREFOUT = 2.2F 0.583 0.575 1.227 1.219 0.595 0.587 1.246 1.238 0.607 0.599 1.265 1.257 V V V V VMSET/MODE = H, CREFOUT = 2.2F VMSET/MODE = H, CREFOUT = 2.2F 0.600 1.250 V V VPGVPG+ IPGLKG Fraction of the set point; ~3s noise filter Fraction of the set point; ~3s noise filter VPULLUP = 5.0V (Note 11) IPGOOD = 4mA CDEL = 0.1F CDEL threshold = 2.5V -14 9 -10 125 2 2.5 -8 16 1 0.5 % % A V ms A V
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Electrical Specifications
Operating Conditions: VIN = 12V, PVCC shorted with VCC5, TA = +25C. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) SYMBOL TEST CONDITIONS CREFOUT = 2.2F MIN (Note 12) 20 TYP MAX (Note 12) UNITS mA
PARAMETER Current Drive Capability VOLTAGE MARGINING Voltage Margining Range (Note 10) CDEL Current for Voltage Margining Slew Time ISET1 on FB Pin
-10 CDEL = 0.1F, VMSET = 330k VMSET = 330k, GPIO1 = L GPIO2 = H VMSET = 330k, GPIO1 = H GPIO2 = L -
100 2.5 7.48
+10 -
% A ms A
ISET2 on FB Pin
-
7.48
-
A
THERMAL SHUTDOWN Shutdown Temperature (Note 10) Thermal Shutdown Hysteresis (Note 10) NOTES: 7. The operating supply current and shutdown current specifications for 5V input are the same as VIN supply current specifications, i.e., 5.6V to 28V input conditions. These should also be tested with part configured for 5V input configuration, i.e., VIN = VCC5 = PVCC = 5V. 8. This is the VCC current consumed when the device is active but not switching. Does not include gate drive current. 9. When the input voltage is 5.6V to 28V at VIN pin, the VCC5 pin provides a 5V output capable of 50mA (max) total from the internal LDO. When the input voltage is 5V, VCC5 pin will be used as a 5V input, the internal LDO regulator is disabled and the VIN must be connected to the VCC5. In both cases the PVCC pin should always be connected to VCC5 pin (refer to "Pin Descriptions" on page 11 for more details). 10. Limits established by characterization and are not production tested. 11. It is recommended to use VCC5 as the pull-up source. 12. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 150 20 C C
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Typical Performance Curves
0.604 320
0.602 FSW (kHz) -15 10 35 TEMPERATURE (C) 60 85
310
VREF (V)
0.600
300
0.598
290
0.596
280
0.594 -40
270 -40
-15
10 35 TEMPERATURE (C)
60
85
FIGURE 1. VREF vs TEMPERATURE
94 1.15 IOCSET NORMALIZED EFFICIENCY (%) 92 90 88 86 84 82 0.85 -40 -15 10 35 TEMPERATURE (C) 60 85 80 0
FIGURE 2. VSW vs TEMPERATURE
IOUT = 5A
1.05
0.95
5
10
15 VIN (V)
20
25
30
FIGURE 3. IOCSET vs TEMPERATURE
FIGURE 4. EFFICIENCY vs VIN
+25C, VIN = 28V, IIN = 1.367, IOUT = 10A
FIGURE 5.
FIGURE 6.
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Typical Performance Curves
98 96 EFFICIENCY (%) 94 92 90 88 86 84 82 80 0 1 2
(Continued)
VIN = 5V
VIN = 12V
3
4 5 6 LOAD (A)
7
8
9
10
FIGURE 7. EFFICIENCY vs LOAD CURRENT (VOUT = 3.3V)
Pin Descriptions
VIN
FREQUENCY (kHz)
This pin powers the controller and must be decoupled to ground using a ceramic capacitor as close as possible to the VIN pin.
TABLE 1. INPUT SUPPLY CONFIGURATION INPUT 5.5V to 28V PIN CONFIGURATION Connect the input to the VIN pin. The VCC5 pin will provide a 5V output from the internal LDO. Connect PVCC to VCC5.
5V 10% Connect the input to the VCC5 pin. Connect the PVCC and VIN pins to VCC5.
1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0
0
25
50
75 RT (k)
100
125
150
SGND
This pin provides the signal ground for the IC. Tie this pin to the ground plane through the lowest impedance connection.
FIGURE 8. OSCILLATOR FREQUENCY vs RT
FB
This pin is connected to the feedback resistor divider and provides the voltage feedback signal for the controller. This pin sets the output voltage of the converter.
LGATE
This pin provides the PWM-controlled gate drive for the lower MOSFET.
PHASE
This pin is the junction point of the output filter inductor, the upper MOSFET source and the lower MOSFET drain. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection. This pin also provides a return path for the upper gate drive.
COMP
This pin is the error amplifier output pin. It is used as the compensation point for the PWM error amplifier.
PGOOD
This pin provides a power good status. It is an open collector output used to indicate the status of the output voltage.
UGATE
This pin provides the PWM-controlled gate drive for the upper MOSFET.
RT
This is the oscillator frequency selection pin. Connecting this pin directly to VCC5 will select the oscillator free running frequency of 300kHz. By placing a resistor from this pin to GND, the oscillator frequency can be programmed from 100kHz to 1.4MHz. Figure 8 shows the oscillator frequency vs. the RT resistance.
BOOT
This pin powers the upper MOSFET driver. Connect this pin to the junction of the bootstrap capacitor and the cathode of the bootstrap diode. The anode of the bootstrap diode is connected to the PVCC pin.
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CDEL
The PGOOD signal can be delayed by a time proportional to a CDEL current of 2A and the value of the capacitor connected between this pin and ground. A 0.1F will typically provide 125ms delay. When in the Voltage Margining mode, the CDEL current is 100A typical and provides the delay for the output voltage slew rate, 2.5ms typical for the 0.1F capacitor. PGND This pin provides the power ground for the IC. Tie this pin to the ground plane through the lowest impedance connection. PVCC This pin is the power connection for the gate drivers. Connect this pin to the VCC5 pin. VCC5 This pin is the output of the internal 5V LDO. Connect a minimum of 4.7F ceramic decoupling capacitor as close to the IC as possible at this pin. Refer to Table 1.
GPIO1/REFIN
This is a dual function pin. If VMSET/MODE is not connected to VCC5 then this pin serves as GPIO1. Refer to Table 3 for GPIO commands interpretation. To use GPIO1/REFIN as input reference, connect VMSET/MODE to VCC5 and GPIO2 to SGND. Connect the desired reference voltage to the GPIO1/REFIN pin in the range of 0.6V to 1.25V. Connect GPIO1/REFIN and VMSET/MODE pins to VCC5, GPIO2 to SGND, the IC operates with the internal reference and no voltage margining function.
REFOUT
It provides buffered reference output for REFIN. Connect 2.2F decoupling capacitor to this pin.
VMSET/MODE
This pin is a dual function pin. Tie this pin to VCC5 to disable voltage margining. When not tied to VCC5, this pin serves as VMSET. Connect a resistor from this pin to ground to set delta for voltage margining. If voltage margining and external reference tracking mode are not needed, VNSET/MODE, GPIO1/REFIN and GPIO2 all together can be tied directly to ground.
ENSS
This pin provides enable/disable function and soft-start for the PWM output. The output drivers are turned off when this pin is held below 1V.
GPIO2
This is general purpose IO pin for voltage margining. Refer to Table 3.
OCSET
Connect a resistor (ROCSET) and a capacitor from this pin to the drain of the upper MOSFET. ROCSET, an internal 100A current source (IOCSET), and the upper MOSFET on resistance rDS(ON) set the converter overcurrent (OC) trip point.
Exposed Thermal Pad
This pad is electrically isolated. Connect this pad to the signal ground plane using at least five vias for a robust thermal conduction path.
TABLE 2. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION PIN CONFIGURATIONS FUNCTION/MODES Enable Voltage Margining VMSET/MODE REFOUT GPIO1/REFIN GPIO2
Serves as a general Serves as a general Connect a 2.2F Pin Connected to GND with resistor. It capacitor for bypass of purpose I/O. Refer to purpose I/O. Refer to Table 3. Table 3. external reference. is used as VMSET. H Connect a 2.2F capacitor to GND. Connect a 2.2F capacitor to GND. H (Note 14) L
No Voltage Margining. Normal operation with internal reference. Buffered VREFOUT = 0.6V. No Voltage Margining. External reference. Buffered VREFOUT = VREFIN NOTES:
H
Connect to an external reference voltage source (0.6V to 1.25V)
L
13. The GPIO1/REFIN and GPIO2 pins cannot be left floating. 14. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.
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TABLE 3. VOLTAGE MARGINING CONTROLLED BY GPIO1 AND GPIO2 GPIO1 L L H H GPIO2 L H L H VOUT No Change +VOUT -VOUT Ignored
IOUT PHASE VOUT
ENSS
Functional Description
Initialization
The ISL6420A automatically initializes upon receipt of power. The Power-On Reset (POR) function monitors the internal bias voltage generated from LDO output (VCC5) and the ENSS pin. The POR function initiates the soft-start operation after the VCC5 exceeds the POR threshold. The POR function inhibits operation with the chip disabled (ENSS pin <1V). The device can operate from an input supply voltage of 5.5V to 28V connected directly to the VIN pin using the internal 5V linear regulator to bias the chip and supply the gate drivers. For 5V 10% applications, connect VIN to VCC5 to bypass the linear regulator.
FIGURE 10. TYPICAL OVERCURRENT HICCUP MODE
Overcurrent Protection
The overcurrent function protects the converter from a shorted output by using the upper MOSFET's ON-resistance, rDS(ON) to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor connected to the drain of the upper FET and the OCSET pin programs the overcurrent trip level. The PHASE node voltage will be compared against the voltage on the OCSET pin, while the upper FET is on. A current (100A typically) is pulled from the OCSET pin to establish the OCSET voltage. If PHASE is lower than OCSET while the upper FET is on then an overcurrent condition is detected for that clock cycle. The upper gate pulse is immediately terminated, and a counter is incremented. If an overcurrent condition is detected for 8 consecutive clock cycles, and the circuit is not in soft-start, the ISL6420A enters into the soft-start hiccup mode. During hiccup, the external capacitor on the ENSS pin is discharged. After the capacitor is discharged, it is released and a soft-start cycle is initiated. There are three dummy soft-start delay cycles to allow the MOSFETs to cool down, to keep the average power dissipation in hiccup mode at an acceptable level. At the fourth soft-start cycle, the output starts a normal soft-start cycle, and the output tries to ramp. During soft-start, pulse termination current limiting is enabled, but the 8-cycle hiccup counter is held in reset until soft-start is completed. Figure 10 shows the overcurrent hiccup mode. The overcurrent function will trip at a peak inductor current (IOC) determined from Equation 1, where IOCSET is the internal OCSET current source.
I OCSET * R OCSET I OC = -------------------------------------------------r DS ( ON ) (EQ. 1)
Soft-Start/Enable
The ISL6420A soft-start function uses an internal current source and an external capacitor to reduce stresses and surge current during start-up. When the output of the internal linear regulator reaches the POR threshold, the POR function initiates the soft-start sequence. An internal 10A current source charges an external capacitor on the ENSS pin linearly from 0V to 3.3V. When the ENSS pin voltage reaches 1V typically, the internal 0.6V reference begins to charge following the dv/dt of the ENSS voltage. As the soft-start pin charges from 1V to 1.6V, the reference voltage charges from 0V to 0.6V. Figure 9 shows a typical soft-start sequence.
VIN = 28V, VOUT = 3.3V, IOUT = 10A
FIGURE 9. TYPICAL SOFT-START WAVEFORM
The OC trip point varies mainly due to the upper MOSFETs rDS(ON) variations. To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from Equation 1 with:
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1. The maximum rDS(ON) at the highest junction temperature. 2. Determine I OC for I OC > I OUT ( MAX ) + ( I ) 2 , where I is the output inductor ripple current. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage.
VIN = 12V, VOUT = 3.3V, NO LOAD
Voltage Margining
The ISL6420A has a voltage margining mode that can be used for system testing. The voltage margining percentage is resistor selectable up to 10%. The voltage margining mode can be enabled by connecting a margining set resistor from VMSET pin to ground and using the control pins GPIO1/2 to toggle between positive and negative margining (Refer to Table 2). With voltage margining enabled, the VMSET resistor to ground will set a current, which is switched to the FB pin. The current will be equal to 2.468V divided by the value of the external resistor tied to the VMSET pin. Use a resistor in the range of 150k to 400k for VMSET resistor.
2.468V I VM = ----------------------R VMSET R FB V VM = 2.468V ----------------------R VMSET (EQ. 2)
FIGURE 12A.
VIN = 12V, VOUT = 3.3V, NO LOAD
(EQ. 3)
The power supply output increases when GPIO2 is HIGH and decreases when GPIO1 is HIGH. The amount that the output voltage of the power supply changes with voltage margining, will be equal to 2.468V x the ratio of the external feedback resistor and the external resistor tied to VMSET. Figure 11 shows the positive and negative margining for a 3.3V output, using a 20.5k feedback resistor and using various VMSET resistor values.
3.7 3.6 3.5 VOUT (V) 3.4 3.3 3.2 3.1 3.0 2.9 2.8 150 175 200 225 250 275 300 325 350 375 400 RVMSET (k)
FIGURE 12B.
VIN = 12V, VOUT = 3.3V, IOUT = 10A
FIGURE 11. VOLTAGE MARGINING vs. VMSET RESISTANCE
FIGURE 13. PGOOD DELAY
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FN9169.4 December 4, 2009
ISL6420A
The slew time of the current is set by an external capacitor on the CDEL pin, which is charged and discharged with a 100A current source. The change in voltage on the capacitor is 2.5V. This same capacitor is used to set the PGOOD active delay after soft-start. When PGOOD is low, the internal PGOOD circuitry uses the capacitor and when PGOOD is high, the voltage margining circuit uses the capacitor. The slew time for voltage margining can be in the range of 300s to 2ms.
Undervoltage
If the voltage on the FB pin is less than 15% of the reference voltage for 8 consecutive PWM cycles, then the circuit enters into soft-start hiccup mode. This mode is identical to the overcurrent hiccup mode.
Overvoltage Protection
If the voltage on the FB pin exceeds the reference voltage by 15%, the lower gate driver is turned on continuously to discharge the output voltage. If the overvoltage condition continues for 32 consecutive PWM cycles, then the chip is turned off with the gate drivers tri-stated. The voltage on the FB pin will fall and reach the 15% undervoltage threshold. After 8 clock cycles, the chip will enter soft-start hiccup mode. This mode is identical to the overcurrent hiccup mode.
External Reference/DDR Supply
The voltage margining can be disabled by connecting the VMSET/MODE to VCC5. In this mode, the chip can be configured to work with an external reference input and provide a buffered reference output. If VMSET/MODE pin and the GPIO1/REFIN pin are both tied to VCC5, then the internal 0.6V reference is used as the error amplifier non-inverting input. The buffered reference output on REFOUT will be 0.6V 0.01V, capable of sourcing 20mA and sinking up to 50A current with a 2.2F capacitor connected to the REFOUT pin. If the VMSET/MODE pin is tied to high but GPIO1/REFIN is connected to an external voltage source between 0.6V to 1.25V, then this external voltage is used as the reference voltage at the positive input of the error amplifier. The buffered reference output on REFOUT will be Vrefin 0.01V, capable of sourcing 20mA and sinking up to 50A current with a 2.2F capacitor on the REFOUT pin.
Gate Control Logic
The gate control logic translates generated PWM control signals into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operational conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through.
Power-Good
The PGOOD pin can be used to monitor the status of the output voltage. PGOOD will be true (open drain) when the FB pin is within 10% of the reference and the ENSS pin has completed its soft-start ramp. Additionally, a capacitor on the CDEL pin will set a delay for the PGOOD signal. After the ENSS pin completes its soft-start ramp, a 2A current begins charging the CDEL capacitor to 2.5V. The capacitor will be quickly discharged before PGOOD goes high. The programmable delay can be used to sequence multiple converters or as a LOW-true reset signal. If the voltage on the FB pin exceeds 10% of the reference, then PGOOD will go low after 1s of noise filtering.
Start-up into Pre-Biased Load
The ISL6420A is designed to power-up into a pre-biased load. This is achieved by transitioning from Diode Emulation mode to a Forced Continuous Conduction mode during start-up. The lower gate turns ON for a short period of time and the voltage on the phase pin is sensed. When this goes negative the lower gate is turned OFF and remains OFF till the next cycle. As a result, the inductor current will not go negative during soft-start and thus will not discharge the pre-biased load. The waveform for this condition is shown in Figure 14.
Over-Temperature Protection
The IC is protected against over-temperature conditions. When the junction temperature exceeds +150C, the PWM shuts off. Normal operation is resumed when the junction temperature is cooled down to +130C.
Shutdown
When ENSS pin is below 1V, the regulator is disabled with the PWM output drivers tri-stated. When disabled, the IC power will be reduced. 15
FN9169.4 December 4, 2009
ISL6420A
VIN = 12V, VOUT = 3.3V at 25mA LOAD
VIN
ISL6420A
UGATE PHASE CIN LGATE GND Q2 D2 Q1
LO
VOUT
CO
RETURN
FIGURE 14. PREBIASED OUTPUT AT 25mA LOAD
FIGURE 15. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. Figure 15 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 15 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the ISL6420A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs' gate and source connections from the ISL6420A must be sized to handle up to 1A peak current. Figure 16 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the ENSS PIN and locate the capacitor, Css close to the SS pin because the internal current source is only 10A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins.
BOOT CBOOT D1 +VIN Q1 L O
ISL6420A
ENSS
VOUT LOAD
PHASE +5V VCC CVCC Q2 CO
CSS GND
FIGURE 16. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES
Feedback Compensation
Figure 17 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC.
16
FN9169.4 December 4, 2009
LOAD
ISL6420A
VIN OSC PWM COMPARATOR VOSC + DRIVER LO DRIVER PHASE CO VOUT
Compensation Break Frequency Equations
1 F Z1 = ---------------------------------2 * R 2 * C1 1 F P1 = -----------------------------------------------------C1 * C2 2 * R2 * --------------------- C1 + C2 1 F Z2 = ----------------------------------------------------2 * ( R1 + R3 ) * C3 1 F P2 = ---------------------------------2 * R3 * C3 (EQ. 6)
-
(EQ. 7)
ESR (PARASITIC) ZFB VE/A + ERROR AMP
(EQ. 8)
-
ZIN REFERENCE
(EQ. 9)
1. Pick Gain (R2/R1) for desired converter bandwidth
DETAILED COMPENSATION COMPONENTS ZFB ZIN R2 C3 R3 R1 VOUT
C2 C1
3. Place 2ND Zero at Filter's Double Pole 4. Place 1ST Pole at the ESR Zero
2. Place 1ST Zero Below Filter's Double Pole (~75% FLC)
5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier's Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary Figure 18 shows an asymptotic plot of the DC/DC converter's gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 18. Using the previously mentioned guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Loop Gain is constructed on the log-log graph of Figure 18 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain.
100 80 60 GAIN (dB) 40 20 0 MODULATOR GAIN FLC 10 100 1k 10k FESR 100k 1M 20LOG (R2/R1) OPEN LOOP ERROR AMP GAIN FZ1 FZ2 FP1 FP2
COMP
+
FB R4 REF
ISL6420A
R 1 V OUT = V REF x 1 + ------ R 4 FIGURE 17. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN
Modulator Break Frequency Equations
1 F LC = -------------------------------------2 * L O * C O 1 F ESR = -------------------------------------------2 * ( ESR * C O ) (EQ. 4)
(EQ. 5)
The compensation network consists of the error amplifier (internal to the ISL6420A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180. The following equations relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 17. Use the following guidelines for locating the poles and zeros of the compensation network.
20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN 10M
-20 -40 -60
FREQUENCY (Hz)
FIGURE 18. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
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FN9169.4 December 4, 2009
ISL6420A
The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45. Include worst case component variations when determining phase margin. current and the output capacitors ESR. The ripple voltage and current are approximated by Equations 10 and 11:
V IN - V OUT V OUT I L = ------------------------------- --------------Fs x L V IN V OUT = I L ESR (EQ. 10) (EQ. 11)
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1.0F ceramic capacitors in the 1206 surface-mount package. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Increasing the value of inductance reduces the ripple current and voltage. However, larger inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6420A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. Equations 12 and 13 give the approximate response time interval for application and removal of a transient load:
L O x I TRAN t RISE = ------------------------------V IN - V OUT L O x I TRAN t FALL = -----------------------------V OUT (EQ. 12)
(EQ. 13)
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 x
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transients. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple 18
FN9169.4 December 4, 2009
ISL6420A
greater than the maximum input voltage and a voltage rating of 1.5 x is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. Equation 14 shows a more specific formula for determining the input ripple:
I RMS = I MAX ( D - D )
2
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency will drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage.
(EQ. 14)
For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The ISL6420A requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see Equations 15 and 16). Only the upper MOSFET has switching losses, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on.
2 1 P UFET = I O r DS ( ON ) D + -- I O V IN t sw f sw 2
(EQ. 15)
P LFET = I O r DS ( ON ) ( 1 - D )
2
(EQ. 16)
Where D is the duty cycle = Vo/VIN, tSW is the switching interval, and fSW is the switching frequency. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse recovery of the lower MOSFET's body diode. The gate-charge losses are dissipated by the ISL6420A and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
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FN9169.4 December 4, 2009
ISL6420A
Package Outline Drawing
L20.4x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/06
4X 4.00 A B 6 PIN 1 INDEX AREA 15 1 16 2.0 6 PIN #1 INDEX AREA
16X 0.50 20
2 . 10 0 . 15 4.00
11
5
(4X)
0.15 10 6 0.10 M C A B 4 0.25 +0.05 / -0.07 20X 0.6 +0.15 / -0.25
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X" 0.10 C C BASE PLANE ( 3. 6 TYP ) ( 2. 10 ) ( 20X 0 . 5 ) SEATING PLANE 0.08 C
0 . 90 0 . 1
SIDE VIEW
( 20X 0 . 25 )
C
0 . 2 REF
5
( 20X 0 . 8)
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
20
FN9169.4 December 4, 2009
ISL6420A Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M20.15
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) SYMBOL A A1 A2 B C D
A2
INCHES MIN 0.053 0.004 0.008 0.007 0.337 0.150 MAX 0.069 0.010 0.061 0.012 0.010 0.344 0.157
MILLIMETERS MIN 1.35 0.10 0.20 0.18 8.56 3.81 MAX 1.75 0.25 1.54 0.30 0.25 8.74 3.98 NOTES 9 3 4 5 6 7 8 Rev. 1 6/04
h x 45
e
B 0.17(0.007) C A M B S M
A1
E
C
0.10(0.004)
e H h L N
0.025 BSC 0.228 0.0099 0.016 20 0 8 0.244 0.0196 0.050
0.635 BSC 5.80 0.26 0.41 20 0 6.19 0.49 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN9169.4 December 4, 2009

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